A high level modeling system (HLMS) is a software tool in which electronic designs can be described, simulated, and translated by machine into a design realization. An HLMS provides a higher level of abstraction for describing an electronic circuit than a hardware description language (HDL) simulation environment such as the ModelSim environment from the Model Technology company. An HLMS generally provides a mathematical representation of signals as compared to standard logic vectors in a hardware description language (HDL). It is desirable for the high-level abstractions to be precisely correlated with the ultimate implementation representation, both in simulation semantics and in implementation. The Xilinx System Generator tool for DSP (Sysgen) and the MathWorks' Simulink and MATLAB environments are examples of such HLMSs.
An HLMS for electronic circuit design generally offers abstractions that are not available in traditional HDLs. For example, an HLMS is likely to offer abstractions that relate to signal propagation and signal state, while an HDL may support a detailed representation that more closely models a realized electronic circuit. An electronic design modeled in an HLMS may be viewed as a collection of components that communicate through signals. Signals are discrete, time-varying sequences of values. An HLMS generally provides abstractions to support implementing synchronous designs without requiring the specification of explicit references to clocks or clock signals. Instead of providing a detailed, event driven simulation, an HLMS may also provide abstractions wherein clock-synchronous state changes are scheduled to occur at regular intervals and in which there is no notion of the timing characteristics related to the intended implementation as an electronic circuit. In further support of creating high-level designs, an HLMS may also represent state in terms of numerical (or other abstract) values instead of representing state in a detailed format analogous to standard logic vectors.
An HLMS such as Sysgen also has the capability to generate objects for co-simulation using a hardware platform. Co-simulation generally refers to dividing a design into portions and simulating the portions on two or more platforms. There are different types of platforms on which designs may be co-simulated.
Example co-simulation platforms include both software-based and hardware-based systems. The Modelsim simulator and the NC-SIM simulator from Cadence are example software-based systems, and the Wildcard and Benone hardware-based platforms from Annapolis Microsystems and Nallatech, respectively, are example hardware-based systems. The WildCard and Benone board are often used for algorithm exploration and design prototyping and include programmable logic devices (PLDs). In software-based co-simulations, the user may perform a behavioral simulation or perform simulation using a synthesized and mapped version of the design.
In a hardware-based system, a portion of the design is emulated on a hardware platform that includes a programmable logic device (PLD), such as a field programmable gate array (FPGA). Co-simulating on a hardware platform may be used to reduce the time required for a simulation run. Hardware co-simulation also may be used to support real-time hardware debugging.
In co-simulation involving an HLMS and a hardware-based co-simulation engine, interactions between the HLMS and hardware-based co-simulation engines may introduce significant overhead and thereby significantly reduce simulation performance. The HLMS executing on a host workstation is responsible for controlling the FPGA during hardware co-simulation and does so by issuing control commands, providing input data, and retrieving output data from the hardware-based co-simulation engine. The overhead introduced in issuing commands and transmitting data may be considerable. For example, when the HLMS issues a command to the hardware-based co-simulation engine, a software device driver is called by the HLMS and the command is transmitted across the communication link.
Overhead associated with transactions between the HLMS and hardware-based co-simulation engine may degrade simulation performance. For example, the HLMS communicates with the hardware-based co-simulation engine for each input/output (I/O) event for a block simulated on the hardware-based co-simulation engine and also when the hardware-based co-simulation engine needs to be clocked to synchronize with the HLMS. Each transaction may involve a small amount of data. The combination of a large number of transactions involving small amounts of data may result in a significant portion of the simulation time being spent on the overhead associated with these transactions.
The present invention may address one or more of the above issues.